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DATA SHEET
MOS INTEGRATED CIRCUIT
PD43257B
256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT
Description
The PD43257B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And the PD43257B has two chip enable pins (/CE1, CE2) to extend the capacity. The PD43257B is packed in 28-pin PLASTIC DIP and 28-pin PLASTIC SOP.
Features
* 32,768 words by 8 bits organization * Fast access time: 70, 85 ns (MAX.) * Low VCC data retention: 2.0 V (MIN.) * Two Chip Enable inputs: /CE1, CE2
Part number Access time ns (MAX.) Operating supply Operating ambient voltage V temperature C 0 to 70 At operating mA (MAX.) 45 45 Supply current At standby At data retention
A (MAX.)
50 15
A (MAX.) Note
3 2
PD43257B-xxL PD43257B-xxLL
70, 85
4.5 to 5.5
Note TA 40 C, VCC = 3.0 V
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. M10693EJ9V0DS00 (9th edition) Date Published June 2006 NS CP (K) Printed in Japan
1992
PD43257B
Ordering Information
Part number Package Access time ns (MAX.) Supply current A (MAX.) At standby 50 At data retention 3
Note
Remark
PD43257BCZ-70L PD43257BCZ-85L PD43257BCZ-70LL PD43257BCZ-85LL PD43257BGU-70L PD43257BGU-85L PD43257BGU-70LL PD43257BGU-85LL PD43257BGU-70L-A PD43257BGU-85L-A PD43257BGU-70LL-A PD43257BGU-85LL-A
28-pin PLASTIC DIP (15.24 mm (600))
70 85 70 85
L version
15
2
LL version
28-pin PLASTIC SOP (11.43 mm (450))
70 85 70 85
50
3
L version
15
2
LL version
28-pin PLASTIC SOP (11.43 mm (450))
70 85 70 85
50
3
L version
15
2
LL version
Note TA 40 C, VCC = 3.0 V Remark Products with -A at the end of the part number are lead-free products.
2
Data Sheet M10693EJ9V0DS
PD43257B
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-pin PLASTIC DIP (15.24 mm (600)) [ PD43257BCZ-xxL ] [ PD43257BCZ-xxLL ]
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC /WE A13 A8 A9 A11 CE2 A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4
A0 - A14 I/O1 - I/O8 /CE1 CE2 /WE VCC GND
: Address inputs : Data inputs / outputs : Chip Enable 1 : Chip Enable 2 : Write Enable : Power supply : Ground
Remark Refer to Package Drawings for the 1-pin marking.
Data Sheet M10693EJ9V0DS
3
PD43257B
28-pin PLASTIC SOP (11.43 mm (450)) [ PD43257BGU-xxL ] [ PD43257BGU-xxLL ] [ PD43257BGU-xxL-A ] [ PD43257BGU-xxLL-A ]
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC /WE A13 A8 A9 A11 CE2 A10 /CE1 I/O8 I/O7 I/O6 I/O5 I/O4
A0 - A14 I/O1 - I/O8 /CE1 CE2 /WE VCC GND
: Address inputs : Data inputs / outputs : Chip Enable 1 : Chip Enable 2 : Write Enable : Power supply : Ground
Remark Refer to Package Drawings for the 1-pin marking.
4
Data Sheet M10693EJ9V0DS
PD43257B
Block Diagram
A0 A14
Address buffer
Row decoder
Memory cell array 262,144 bits
I/O1 I/O8 Input data controller
Sense amplifier / Switching circuit Column decoder
Output data controller
Address buffer
/CE1 CE2
/WE VCC GND
Truth Table
/CE1 H x L L CE2 x L H H /WE x x H L Read Write DOUT DIN ICCA Mode Not selected I/O High impedance Supply current ISB
Remark x : VIH or VIL
Data Sheet M10693EJ9V0DS
5
PD43257B
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating -0.5 -0.5
Note
Unit V V C C
to +7.0
Note
to VCC + 0.5
0 to 70 -55 to +125
Note -3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 4.5 2.2 -0.3 0
Note
TYP. 5.0
MAX. 5.5 VCC+0.5 +0.8 70
Unit V V V C
Note -3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O Test conditions VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 5 8 Unit pF pF
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested.
6
Data Sheet M10693EJ9V0DS
PD43257B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition
PD43257B-xxL
MIN. TYP. MAX. +1.0
PD43257B-xxLL
MIN. -1.0 TYP. MAX. +1.0
Unit
Input leakage current I/O leakage current Operating supply current
ILI
VIN = 0 V to VCC
-1.0
A
ILO
VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL
-1.0
+1.0
-1.0
+1.0
A
ICCA1
/CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA
PD43257B-70 PD43257B-85
45 45 10 10
45 45 10 10
mA
ICCA2 ICCA3
/CE1 = VIL, CE2 = VIH, II/O = 0 mA /CE1 0.2 V, CE2 VCC - 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V
Standby supply current
ISB ISB1 ISB2
/CE1 = VIH or CE2 = VIL, /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V CE2 0.2 V IOH = -1.0 mA IOH = -0.1 mA IOL = 2.1 mA 2.4 VCC-0.5 1.0 1.0
3 50 50 2.4 VCC-0.5 0.4 0.5 0.5
3 15 15
mA
A
High level output voltage Low level output voltage
VOH1 VOH2 VOL
V
0.4
V
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time.
Data Sheet M10693EJ9V0DS
7
PD43257B
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ PD43257B-70L, PD43257B-85L, PD43257B-70LL, PD43257B-85LL ] Input Waveform (Rise and Fall Time 5 ns)
2.2 V 1.5 V 0.8 V Test points 1.5 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2.
Figure 1 (tAA, tCO1, tCO2, tOH)
+5 V
Figure 2 (tLZ1, tLZ2, tHZ1, tHZ2, tWHZ, tOW)
+5 V
1.8 k I/O (Output) 990 100 pF CL I/O (Output) 990
1.8 k
5 pF CL
Remark CL includes capacitance of the probe and jig, and stray capacitance.
8
Data Sheet M10693EJ9V0DS
PD43257B
Read Cycle
Parameter
Symbol
PD43257B-70
MIN. MAX.
PD43257B-85
MIN. 85 MAX.
Unit
Condition
Read cycle time Address access time /CE1 access time CE2 access time Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance
tRC tAA tCO1 tCO2 tOH tLZ1 tLZ2 tHZ1 tHZ2
70 70 70 70 10 10 10 30 30
ns 85 85 85 ns ns ns ns ns ns 30 30 ns ns Note 2 Note 1
10 10 10
Notes 1. See the output load shown in Figure 1. 2. See the output load shown in Figure 2.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle Timing Chart
tRC
Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH
CE2 (Input)
tCO2 tLZ2 tHZ2 Data out
I/O (Output)
High impedance
Remark
In read cycle, /WE should be fixed to high level.
Data Sheet M10693EJ9V0DS
9
PD43257B
Write Cycle
Parameter
Symbol
PD43257B-70
MIN. MAX.
PD43257B-85
MIN. 85 70 70 70 0 65 0 35 0 MAX.
Unit
Condition
Write cycle time /CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write
tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW
70 50 50 50 0 55 0 30 0 30 10
ns ns ns ns ns ns ns ns ns 30 ns ns Note
10
Note See the output load shown in Figure 2.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
10
Data Sheet M10693EJ9V0DS
PD43257B
Write Cycle Timing Chart 1 (/WE Controlled)
tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M10693EJ9V0DS
11
PD43257B
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC Address (Input)
tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input)
tCW1
tWR
tDW High impedance I/O (Input) Data in
tDH High impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output.
Remark
Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
12
Data Sheet M10693EJ9V0DS
PD43257B
Write Cycle Timing Chart 3 (CE2 Controlled)
tWC Address (Input)
tCW1 /CE1 (Input)
tAS CE2 (Input) tAW tWP /WE (Input)
tCW2
tWR
tDW High impedance I/O (Input) Data in
tDH High impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output.
Remark
Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
Data Sheet M10693EJ9V0DS
13
PD43257B
Low VCC Data Retention Characteristics (TA = 0 to 70 C)
Parameter Symbol Test Condition
PD43257B-xxL
MIN. TYP. MAX. 5.5
PD43257B-xxLL
MIN. 2.0 TYP. MAX. 5.5
Unit
Data retention supply voltage
VCCDR1
/CE1 VCC - 0.2 V, CE2 VCC - 0.2 V CE2 0.2 V VCC = 3.0 V, /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V VCC = 3.0 V, CE2 0.2 V
2.0
V
VCCDR2 Data retention supply current ICCDR2 Chip deselection to data retention mode Operation recovery time tR tCDR ICCDR1
2.0 0.5
5.5 20
Note1
2.0 0.5
5.5 7
Note2
A
0.5 0
20
Note1
0.5 0
7
Note2
ns
5
5
ms
Notes 1. 3 A (TA 40 C) 2. 2 A (TA 40 C), 1 A (TA 25 C)
14
Data Sheet M10693EJ9V0DS
PD43257B
Data Retention Timing Chart
(1) /CE1 Controlled
tCDR VCC 4.5 V Data retention mode tR
/CE1 VIH (MIN.) VCCDR (MIN.) /CE1 VCC - 0.2 V
VIL (MAX.)
GND
Remark
On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 VCC - 0.2 V or CE2 0.2 V. The other pins (Address, I/O, /WE) can be in high impedance state.
(2) CE2 Controlled
tCDR VCC 4.5 V Data retention mode tR
VIH (MIN.) VCCDR (MIN.) CE2
VIL (MAX.) CE2 0.2 V GND
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE) can be in high impedance state.
Data Sheet M10693EJ9V0DS
15
PD43257B
Package Drawings
28-PIN PLASTIC DIP (15.24 mm (600))
28 15
1 A
14
J I
K L
F D H G
NOTES
C N
M
B M R
1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 38.10 MAX. 2.54 MAX. 2.54 (T.P.) 0.500.10 1.2 MIN. 3.60.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.25 015 P28C-100-600A1-2
16
Data Sheet M10693EJ9V0DS
PD43257B
28-PIN PLASTIC SOP (11.43 mm (450))
28 15
detail of lead end
P
1 A F G
14
H I S J
C D E
NOTE
N
M
S B K
L
M
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 18.0 +0.6 -0.05 1.27 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.20.1 2.95 MAX. 2.550.1 11.80.3 8.40.1 1.70.2 0.220.05 0.70.2 0.12 0.10 3 +7 -3 P28GU-50-450A-4
Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
Data Sheet M10693EJ9V0DS
17
PD43257B
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD43257B.
Types of Surface Mount Device
PD43257BGU-xxL PD43257BGU-xxLL
: 28-pin PLASTIC SOP (11.43 mm (450)) : 28-pin PLASTIC SOP (11.43 mm (450))
PD43257BGU-xxL-A : 28-pin PLASTIC SOP (11.43 mm (450)) PD43257BGU-xxLL-A : 28-pin PLASTIC SOP (11.43 mm (450))
Types of Through Hole Mount Device
PD43257BCZ-xxL PD43257BCZ-xxLL
: 28-pin PLASTIC DIP (15.24 mm (600)) : 28-pin PLASTIC DIP (15.24 mm (600))
Soldering conditions Solder temperature : 260 C or below, Flow time : 10 seconds or below Partial heating method Terminal temperature : 300 C or below, Time : 3 seconds or below (Per one lead)
Soldering process Wave soldering (only to leads)
Caution Do not jet molten solder on the surface of package.
18
Data Sheet M10693EJ9V0DS
PD43257B
Revision History Edition/ Date This edition 9th edition/ Jun. 2006 p.1 Page Previous edition p.1 Deletion - Description of Version X has been deleted. Type of revision Location Description (Previous edition This edition)
Data Sheet M10693EJ9V0DS
19
PD43257B
[ MEMO ]
20
Data Sheet M10693EJ9V0DS
PD43257B
[ MEMO ]
Data Sheet M10693EJ9V0DS
21
PD43257B
[ MEMO ]
22
Data Sheet M10693EJ9V0DS
PD43257B
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet M10693EJ9V0DS
23
PD43257B
* The information in this document is current as of June, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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